1. Field of the Invention
The present invention relates to a general semiconductor device and a method of manufacturing the same, and more specifically, to the structure of an antifuse device which can be electrically programmed, and a method of manufacturing the same.
2. Description of the Related Art
An antifuse device, which is recently focused one of the semiconductor devices, is a switch device which exhibits an electrically non-conductive state generally in an initial state, and is capable of shifting the non-conductive state to a conductive state irreversibly by use of an electrical method.
The antifuse device is used generally in an EPROM (electrically programmable ROM) or in an FPGA (field programmable gate array), which is a type of gate arrays.
An antifuse device usually includes a pair of electrodes formed on two wiring layers different from each other, and an insulating or high-resisting dielectric element inserted between these electrodes.
The dielectric element is programmed (shifting a non-conductive state to a conductive state by insulation breakdown) by applying a high voltage selectively to the electrodes, and wiring layers are electrically connected to each other.
In the case where the antifuse is actually used in the above-mentioned EPROM or FPGA, a plurality of antifuse devices A are arranged in a matrix manner along wirings L1 and L2 provided normal to each other as shown in FIG. 1, or a plurality of antifuse devices A11-A13 and A21-A23 are arranged in a matrix manner set along wirings S1, G1, S2 and G2 with regard to D1, D2 and D3.
With this structure, the antifuse device functions as a parasitic resistance or capacity component, and influences on the circuit speed. Further, the antifuse serves to increase the area of the circuit, and influences on the circuit layout.
Under the above-described circumstances, it is required as the characteristics of the antifuse device that the preprogram capacity, the postprogram resistance (ON resistance), and the area of the device should be all sufficiently small.
It should be noted that an antifuse device can be made of various combinations of electrode materials and dielectric materials; however such various combinations can be categorized mainly into the following three groups:
(1) The type in which a high-concentration diffusion layer formed on a semiconductor substrate is used as a lower electrode;
(2) The type in which a high-concentration polysilicon is used as a lower electrode; and
(3) A metal of Al, TiN, TiW, Mo or the like, formed in a layer located upper than the first Al wiring is used as a lower electrode.
Of these types, types (1) and (2) can be prepared generally by depositing an antifuse film at a high temperature, and therefore they are excellent in terms of the stability of the antifuse film; however their ON resistances are as high as several hundred .OMEGA..
In contrast, with regard to type (3), the On resistance can be lowered to several hundred .OMEGA..
Under these circumstances, since the low-resistance inter-metal-wiring antifuse is advantageous for a high-speed operation of the next generation, at present, the research and development of an inter-metal-wiring antifuse device is being progressed.
Some of the conventional inter-metal-layer antifuse elements will now be described with reference to FIGS. 3 and 4.
FIG. 3 shows a conventional inter-metal-wiring antifuse (which is disclosed in U.S. Pat. No. 5,196,724) used in an FPGA, and the content of this conventional art is as follows.
First, a transistor 162, interlayer insulation films 118 and 119 and a contact hole are formed on a silicon substrate 100 by a general CMOS process.
After that, aluminum is sputtered thereon to form a layer of about 600 nm, and then the layer is formed into a first aluminum wiring layer 124 by using a general lithography method and dry etching.
Subsequently, an insulation film is deposited, and then the insulation film is formed into a sufficiently smooth interlayer insulation layer 132 by a general resist etch back method.
Next, TiW is sputtered to formed a layer of 200 nm on the interlayer insulation film 132, and the layer is patterned in an antifuse formation region in a wiring manner in the direction parallel to the first aluminum wiring layer 124, into a TiW lower electrode wiring 138.
Subsequently, an insulation film 140 having a thickness of 300 nm is deposited, and antifuse vias 144a and 144b and regular vias 198a and 198b are formed at predetermined positions on the TiW lower electrode wiring 138.
After that, an amorphous silicon layer 146 having a thickness of 160 nm is deposited by the PECVD method, and this layer is patterned so that portions thereof remain only on the antifuse vias 144a and 144b.
Subsequently, a silicon oxide film having a thickness of 200 nm is deposited, and then this film is etched by the RIE method, to form spacers 166 and 168 on the side walls of the antifuse vias 144a and 144b.
Next, with use of the regular lithography method and the etching method, the insulation film 140 and the interlayer insulation film 132 are opened to form vias 200a and 200b both of which reach the first Al wiring layer 124.
It should be noted that the first Al wiring layer 124 and the TiW lower electrode wiring 38 are connected to each other by means of the vias 200a and 200b and the vias 198a and 198b.
After the formation of the vias 200a and 200b, a TiW layer 170 having a thickness of 200 nm and an Al layer 172 having a thickness of 800 nm are formed by sputtering, and then these layers are patterned by a general method into a second wiring layer and an upper electrode (not shown).
Thus, an FPGA having an inter-metal-wiring antifuse device is realized.
FIG. 4 shows another conventional inter-metal-layer antifuse device (disclosed in Jpn. Pat. Appln. KOKAI Publication No. 7-22513 by the same assignee as the present application), the content of this conventional art is as follows.
First, a transistor 43 and interlayer insulation films 44 and 45 are formed on a silicon substrate 31 by means of the regular CMOS process.
After that, a Ti/TiN layer 46 having a Ti portion 20 nm thick and a TiN portion 70 nm thick is formed by sputtering, an aluminum layer 32 having a thickness of 800 nm is formed by sputtering thereon, and a Ti/TiN layer 47 having a Ti portion 20 nm thick and a TiN portion 70 nm is formed by sputtering, thus forming a Ti/TiN/Al/Ti/TiN laminate (46, 32, 47).
This laminate is formed into a first wiring layer (46, 32, 47) by the general lithography method and the RIE method.
In a region where an antifuse device is formed, the laminate serves as an antifuse lower electrode.
Next, an SiO.sub.2 insulation film 34 having a thickness of 400 nm is deposited by the PECVD, and the portion of the SiO.sub.2 insulation film 34, which located on the antifuse region, is selectively etched by the regular lithography and the RIE, thus forming a tapered opening portion 35 (antifuse via).
Subsequently, an SiN layer having a thickness of 20 nm is deposited by the plasma CVD method, and then a TiN layer 48 having a thickness of 100 nm is formed thereon by sputtering.
After that, with use of the regular method, patterning is carried out so that the SiN layer 20 and the TiN layer 48 remain only in the antifuse region.
Next, for example, a TEOS oxide film is deposited, and after smoothing the TEOS oxide film by the resist etch back method, an interlayer insulation film 49 is deposited.
Then, an opening portion 40 is formed in the antifuse portion and the regular via portion by the regular lithography and the RIE method.
Subsequently, a Ti/TiN layer 38 serving as a barrier metal underneath the Al layer, and having a Ti portion 20 nm thick and a TiN portion 700 nm thick is formed by sputtering, and a second Al wiring layer 41 is formed thereon by sputtering.
The wiring layer is patterned into a second wiring layer by the regular method.
Further, via a passivation step, an FPGA is formed. In FIG. 4, each of the reference numerals 21, 22, and 23 denotes an insulation film.
However, with the structure of the first prior art example shown in FIG. 3, the following problems arise.
(1) Since the spacers 166 and 168 must be formed so that the amorphous silicon layer 146 serving as an antifuse film is deposited appropriately on the edge of the opening portion, the antifuse vias must be formed larger than usual by the portions of the spacers, thus decreasing the degree of integration as a whole circuit.
(2) Since the TiW lower electrode wiring 138 is provided between the first wiring layer and the second wiring layer, the thickness of the interlayer film between the first wiring layer and the TiW lower electrode wiring layer is decreased, and therefore it is expected that the short-yield of both layers should be lower than usual.
In other words, with the regular resist etch back method, only a limited smoothness can be obtained. For example, in the case of the structure disclosed in U.S. Pat. No. 5,196,724, it can be easily expected that the thickness of the interlayer between the first Al wiring layer 124 and the TiW lower electrode wiring 138, of the antifuse portion, should be remarkably thinner than that between the first Al wiring layer 124 and the second Al layer (not shown) of the transistor region.
In the case where the thickness of the interlayer insulation film between the first Al wiring layer 124 and the TiW lower electrode wiring layer 138 is set at the same as that of the insulation film between the first wiring layer and the second wiring layer of a general CMOS transistor, the insulation film between the first and second wiring layers of the FPGA (antifuse portion) becomes thicker than usual.
As a result, the via between the first and second wiring layers is deepened, and therefore the via yield is decreased as long as the via size is made larger than a regular CMOS.
In the case where the via size is made larger than the regular CMOS, it is only natural that the degree of integration is lowered.
Further, with this structure, a total of three masks, one for forming a special wiring layer, one for opening an antifuse hole, and the other one for patterning an antifuse material, are required, and therefore the processing cost is increased due to a total of three masks which are necessary, and an increase in the number of processing steps.
With the structure of the second prior art example shown in FIG. 4, the problem (2) can be solved since the TiW lower electrode wiring layer used in the first prior art example, and which is a wiring exclusively for an antifuse, is not present.
However, in the second prior art example, the process of forming an antifuse includes two steps each of which makes an opening in the antifuse portion. Therefore, a marginal area must be provided between the first wiring and the opening portion 5, and between the TiN layer 48 and the via 40, resulting in the lowering of the degree of integration.
In this case, the number of masks is increased by two, and although which is slightly better than the case of the first prior art example, the processing cost is increased.
As described above, the conventional proposed inter-metal-wiring antifuse device has a low wiring yield due to the formation of the special wiring layer for the antifuse.
Further, in the conventional antifuse portion, the wiring must be formed at a rule looser than the wiring rule for the regular CMOS transistor, thus lowering the degree of integration.
Further, in order to manufacture the conventional antifuse device, an increased number of masks are involved, thus raising the processing cost.
Therefore, the structure and processing of the conventional inter-metal-wiring antifuse device still need to be improved in terms of wiring yield, the degree of integration, and the cost, in the case where the device is actually applied to an FGPA or the like.